The present invention relates to a system in which a low voltage swing differential global clock network is applied on an integrated circuit chip.
In integrated circuits, inverters may be used to drive clock signals from a generation point where the signals are generated to the various points on an integrated circuit chip. The inverters are distributed throughout the integrated circuit chip, and function as inverting amplifiers which amplify the signals to compensate for any loss of signal occurred during propagation from the generation point at a central location to the various points on the chip.
FIG. 1 shows one exemplary embodiment of a full voltage swing clocking network, where the signals are driven from a generation point at a central location to receiving points at the four corners of an integrated circuit chip. As shown in FIG. 1, signals generated at the central location are driven to the corners, or local ends, through a network. This network, or clock tree 10, radiates from the phase locked loop (PLL) to the local ends, and includes a plurality of inverters 101. Each inverter 101 provides full voltage swing signals from ground to the supply voltage.